This invention relates to a C-MOS device and a process for manufacturing the same and, more particularly, to an improvement of the technology for forming the micropatterns thereon.
As is well known, in C-MOS (Complementary-Metal Oxide Semiconductor) devices, a pair of MOS transistors having p and n channels is formed on the same semiconductor substrate. Particularly, in recent C-MOS devices, the attainment of the technology for forming fine patterns thereon is demanded in association with high density and high integration.
The conventional C-MOS device is manufactured by the process which will be explained hereinbelow with reference to FIGS. 1(a) to1(h).
As shown in FIG. 1(a), for example, a thermal oxide film 2 is grown on an n-type silicon substrate 1 having a surface index (100); and further, a resist pattern 3, a portion of which is removed by photoetching and which forms a well, is formed on the thermal oxide film 2. Thereafter, boron is ion-implanted using the resist pattern 3 as the mask under the conditions of, for instance, a dose amount of 8.5.times.10.sup.12 cm.sup.-2 at 100 keV, thereby forming a boron ion-implantation layer 4 in the substrate 1. Subsequently, as shown in FIG. 1(b), the resist pattern 3 is removed and the ion implantation layer 4 is thermally diffused, for instance, at 1200.degree. C. for 30 hours to form a p-well region 5. Further, after removing the thermal oxide film 2 by etching, a thermal oxide film 6 and a silicone nitride film 7 are again sequentially formed. Then, as shown in FIG. 1(c), the field portions of the silicone nitride film 7 are selectively etched using the photoetching technique to form silicone nitride film patterns 7.sub.a to 7.sub.c.
Next, as shown in FIG. 1(d), a resist pattern 8 which covers the regions other than the p-well region 5 is formed by photoetching. Then, after boron, for instance, is ion-implanted (under an acceleration voltage of 40 keV and a dose amount of 8.times.10.sup.13 cm.sup.-2 using the resist pattern 8 and silicone nitride film pattern 7.sub.b as masks), it is thermally diffused to form a p.sup.- layer 9 which prevents field inversion. Subsequently, as shown in FIG. 1(e), the resist pattern 8 is removed, and a resist pattern 10 which covers the p-well region 5 is formed again by photoetching. After phosphorus, for instance, is ion-implanted under an acceleration voltage of 100 keV and a dose amount of 5.times.10.sup.12 cm.sup.-2 using the resist pattern 10 and silicone nitride film patterns 7.sub.a and 7.sub.c as masks, it is thermally diffused to form an n.sup.- layer 11 for the prevention of field inversion. Next, as shown in FIG. 1(f), the resist pattern 10 is removed; and the semiconductor device is selectively oxidized in a wet atmosphere at a high temperature using the silicone nitride film patterns 7.sub.a to 7.sub.c as the oxidation-resistant masks, thereby forming a field oxide film 12.
Subsequently, as shown in FIG. 1(g), thermal oxide films are grown in the island n-type silicon substrate 1 regions and p-well region 5 which are separated by a field oxide film 12. Further, a polycrystalline silicon film is deposited thereon and phosphorus is diffused in this polycrystalline silicon layer. Then, gate electrodes 13.sub.1 and 13.sub.2 are formed by patterning the polycrystalline silicon layer. After the thermal oxide films are etched using the gate electrodes as masks to form gate oxide films 14.sub.1 and 14.sub.2, boron is ion-implanted in the island substrate 1 region and arsenic is ion-implanted in the island p-well region 5, respectively, thereby forming p.sup.+ -type source and drain regions 15.sub.1 and 16.sub.1 and n.sup.+ -type source and drain regions 15.sub.2 and 16.sub.2. Thereafter, as shown in FIG. 1(h), a CVD-SiO.sub.2 film 17 is deposited on the whole surface in accordance with the ordinary known manner and after contact holes 18.sub.1 to 18.sub.4 are formed therein, the Al film is deposited by evaporation in those respective holes 18.sub.1 -18.sub.4 and Al wirings 19 to 22 are formed by patterning, thereby manufacturing a C-MOS device.
However, the conventional C-MOS device manufactured in this way has the following drawbacks. Namely, the first problem is that an undesirable latch-up phenomenon is caused due to the occurrence of the parasitic pnp transistor which is constituted by the p.sup.+ -source region 15.sub.1 (or drain region 16.sub.1), n-type substrate 1 and p-well region 5, and due to the occurrence of the parasitic npn transistor which is constituted by an n.sup.+ -type source region 15.sub.2 (or drain region 16.sub.2), p-well region 5 and n-type substrate 1. Although this latch-up phenomenon depends upon the resistances of the substrate 1 and well region 5 and upon the carry-over probability of the minority carrier, the carry-over probability between them is determined by the distance between the n-channel and p-channel device regions. Therefore, as the patterns are formed more finely on the device, the latch-up phenomenon is caused more easily, so that the device's characteristics deteriorate. In addition, as shown in FIG. 1(b), the p-well region 5 has a tendency to extend in the direction of the depth of the substrate 1 and to also extend in the lateral direction (for example, when it extends by 10 .mu.m in the direction of the substrate, it also extends by 7 to 8 .mu.m in the lateral direction); therefore, this causes an obstacle which forms fine patterns and causes the deterioration of the degree of integration. Further, as shown in FIGS. 1(d) and 1(e), since ion implantation is performed to prevent field inversion of the n and p channels, the number of photoetching steps in manufacturing the device and the like increases, which has a negative effect in improving productivity. Further, with such a structure as mentioned above, the resistance (.rho..sub.s) of the well portion is relatively high (typically, .rho..sub.s =8 kohms/.quadrature.), so that when a substrate current flows due to the operation of the transistor formed on the well surface, the junction between the well and the region of the opposite conductivity type to the well which was formed on the well surface is biased in the forward direction due to the variation in the potential of the well. As a result, the latch-up phenomenon is caused as mentioned above. In addition, as shown in FIG. 1(b), since the device is subjected to thermal treatment at a high temperature (1200.degree. C.) for a long time (30 hours) when the p-well region 5 is formed, warping occurs in the wafer as the diameter of the wafer becomes larger, making the photoetching step and the like difficult to perform. Also, a crystal defect and the like can occur, causing deterioration of the device.
On the other hand, the conventional C-MOS device manufactured in the manner as described above also has a problem of a soft error, which is caused by a .alpha. rays. That is, in the case where the .alpha. rays enter the p-well 5 of the n-channel transistor section, the electrons produced in the well are absorbed by the n-type substrate 1 due to the potential difference at the pn junction, so that the soft error is suppressed. However, in the case where the .alpha. rays enter the substrate of the p-channel transistor section, since the pn junction, as the p-well, doesn't exist on the substrate side and as the structure to absorb the holes is not present, there is a drawback that the of holes produced are absorbed in the source 15.sub.1, drain 16.sub.1, gate 13.sub.1 of the p-channel transistor, and the like, so that it is difficult to suppress the soft error.
Further, as explained above, in the well structure, since the resistance of the portion of the p-well 5 is relatively high (.rho..sub.s =8 k.OMEGA./.quadrature.), when the substrate current flows due to the operation of the transistor formed on the well surface, the potential in the p-well easily varies locally due to the voltage drop due to the substrate current. Thus, it is possible for the operation margin of the C-MOS device to decrease (in such a case, a malfunction could occur).
On one hand, the C-MOS device used as a circumference circuit and the like of the semiconductor memory device, and having the structure shown in FIG. 2 has been conventionally known. Namely, this device is manufactured in a similar manner as the process shown earlier. In the diagram, a reference numeral 21 denotes, e.g., an n-type silicon substrate and a p-well region 22 is selectively formed on the surface of this substrate 21. A field oxide film 23 is formed on the surface of the silicon substrate 21 which separates between the p-well region 22 and the region which will become a p-channel transistor. In addition, an n.sup.- -type inversion preventing layer 24 is formed on the surface of the boundary of the n-type silicon substrate 21 which is in contact with the field oxide film 23. Also, a p.sup.- -type inversion preventing layer 25 is formed on the surface of the boundary of the p-well region 22 which is in contact with the oxide film 23. A p.sup.+ -type source region 26.sub.1 and a p.sup.+ -type drain region 27.sub.1 which are mutually electrically insulated are formed on the surface of the island substrate 21 region separated by the field oxide film 23. Further, a gate electrode 29.sub.1 is provided through a gate oxide film 28.sub.1 on the substrate 21 which includes at least the channel region between those regions 26.sub.1 and 27.sub.1. A p-channel MOS transistor is constituted by the source and drain regions 26.sub.1 and 27.sub.1 ; gate electrode 29.sub.1 ; etc. Also, an n.sup.+ -type source region 26.sub.2 and an n.sup.+ -type drain region 27.sub.2 which are mutually electrically insulated are formed on the surface of the p-well region 22. Moreover, a gate electrode 29.sub.2 is provided through a gate oxide film 28.sub.2 on the p-well region 22 which includes at least the channel region between those regions 26.sub.2 and 27.sub.2. An n-channel MOS transistor is formed by the source and drain regions 26.sub.2 and 27.sub.2 ; gate electrode 29.sub.2 ; etc. Also, the p.sup.+ -type source region 26.sub.1 is connected to a power supply terminal V.sub.DD ; the n.sup.+ -type source region 26.sub.2 is connected to a ground terminal V.sub.SS ; the respective gate electrodes 29.sub.1 and 29.sub.2 are connected to an input terminal V.sub.in ; and the respective drain regions 27.sub.1 and 27.sub.2 are connected to an output terminal V.sub.out, respectively.
However, in the above-described C-MOS device as shown in FIG. 2, the diffusion layers of the different conductivity types such as the well region 22; source and drain regions 26.sub.1, 26.sub.2, 27.sub.1, and 27.sub.2 ; etc. are provided on the silicon substrate 21. Therefore, it seems as if the bipolar transistors of the npn and pnp types were formed and mutually combined so that an undesirable parasitic thyristor having the pnpn structure could be formed. In reality, however, a vertical npn transistor 30 is parasitically formed in which the n-type silicon substrate 21 is used as the collector, the p-well region 22 is used as the base, and the n.sup.+ -type source region 26.sub.2 (or n.sup.+ -type drain region 27.sub.2) is used as the emitter. Since this parasitic transistor 30 uses, as the base, the p-well region 22 (f=10 .OMEGA.-cm; x.sub.j =10 .mu.m) with a low density which is peculiar to the C-MOS device, it easily has a large current amplification factor (h.sub.FE .perspectiveto.200). This factor is responsible for producing the parasitic thyristor which easily causes the latch-up and soft errors as mentioned above due to noise from the outside. Thus, this causes malfunctions to occur which lead to the destruction of the C-MOS device.
Therefore, many problems can arise if such a C-MOS device as shown in FIG. 2 is used as the circumference circuit of a semiconductor memory device, e.g., of a dynamic RAM.